Semiconductor transistor devices and methods for forming semiconductor transistor devices

ABSTRACT

The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

RELATED PATENT DATA

[0001] This patent is a continuation-in-part of U.S. patent applicationSer. No. ______, filed on Feb. 22, 1996, entitled “SemiconductorProcessing Method of Fabricating Field Effect Transistors”, listing theinventors as Aftab Ahmad and Kirk Prall, and which is now U.S. Pat. No.______.

TECHNICAL FIELD

[0002] This patent pertains to methods of forming graded junctionregions operatively adjacent transistor gates, methods of forming gradedjunction regions operatively adjacent transistor gates of CMOScircuitry, and methods of forming graded junction regions operativelyadjacent peripheral NMOS transistor gates and operatively adjacent thetransistor gates of a memory array. The patent also pertains tosemiconductor transistor devices generally.

BACKGROUND OF THE INVENTION

[0003] This invention grew out of a need to improve the methods ofimplanting graded junction regions within semiconductor devices and tothereby enhance production of integrated circuitry. Some typical typesof graded junction regions are described with reference to FIG. 1.

[0004] In FIG. 1 is shown a semiconductor wafer fragment 10 comprising aportion of a semiconductor wafer material 12. Wafer 12 comprises anupper surface 13. Preferably, the semiconductor material of wafer 12comprises conductively doped polysilicon. Above and within semiconductorwafer 12 is formed a transistor device 14. Device 14 comprises a gate16, source/drain regions 18, and graded junction regions 20 and 22.

[0005] Gate 16 further comprises a gate oxide layer 24, a polysiliconlayer 26, a refractory metal layer 28, an upper oxide layer 29, and acap layer 30. Refractory metal layer 28 typically comprises ametal-silicide, such as tungsten silicide or titanium silicide, and caplayer 30 preferably comprises silicon nitride.

[0006] Gate 16 also comprises opposing lateral sidewalls 32. Sidewallspacers 34 are adjacent sidewalls 32 and comprise a sidewall spacermaterial, preferably silicon nitride. Sidewall spacers 34 comprise alateral thickness “X”, which as measured at about the height of metallayer 28 is typically from about 200 Angstroms to about 1000 Angstroms.

[0007] Also, adjacent lateral sidewalls 32 is a silicon oxide layer 36.Silicon oxide layer 36 is generally formed by oxidizing the polysiliconof gate 16 and the polysilicon of upper surface 13 of wafer 12.

[0008] Source/drain regions 18 contain a conductivity enhancing dopantof a type dictated by the type of transistor device 14. If transistordevice 14 is a P-channel Metal-Oxide Semiconductor (PMOS) field effecttransistor, then source/drain regions 18 will comprise a p-type dopant.If, on the other hand, transistor device 14 is an N-channel Metal-OxideSemiconductor (NMOS) field effect transistor, source/drain regions 18will comprise n-type dopant.

[0009] Graded junction regions 20 and 22 are typically lightly dopeddrain (LDD) regions and halo regions. Generally, and preferably, thegraded junction region extending nearest to gate 16, i.e., region 22,will be a halo region and the other graded junction region, i.e., region20, will be an LDD region. However, the order of the graded junctionregions can be reversed. Also, one or both of the graded junctionregions may be eliminated in various transistor devices.

[0010] The LDD regions comprise conductivity enhancing dopant of thesame conductivity type as the adjacent source/drain regions. Thus, in anNMOS device the LDD regions comprise n-type dopant and in a PMOS devicethe LDD regions comprise p-type dopant. The LDD regions reduce theelectric field under gate 16 and thereby reduce the energy of hotelectrons within transistor device 14. Such reduction in energy canreduce the damage caused to device 14 by hot electrons.

[0011] The halo regions comprise conductivity enhancing dopant of adifferent conductivity type than the adjacent source/drain regions.Thus, in an NMOS device the halo regions comprise a p-type dopant and ina PMOS device the halo regions comprise n-type dopant. The halo regionsare used to improve the punch-through resistance of transistor device14.

[0012] Referring to FIG. 2, a semiconductor wafer fragment 40 isillustrated at a processing step in accordance with the prior art.Fragment 40 comprises a portion of semiconductor wafer material 42. Thesemiconductor material of wafer 42 preferably comprises conductivelydoped polysilicon. The shown wafer fragment 40 is subdivided into threedefined regions: PMOS region 44 (only a portion of which is shown),peripheral NMOS region 46, and memory array region 48 (only a portion ofwhich is shown). Regions 44 and 46 together comprise a definedperipheral region 50 (only a portion of which is shown).

[0013] The semiconductor material of wafer 42 within peripheral NMOSregion 46 and memory array region 48 is typically polysilicon lightlydoped with a p-type impurity. The semiconductor material of wafer 42within PMOS region 44 is typically polysilicon comprising a well 52which is lightly doped with an n-type impurity.

[0014] A series of transistor gates 54, 56, 58 and 60 are provided on atop surface 61 of wafer 42. Gate 54 corresponds to a PMOS transistorgate, gate 56 corresponds to a peripheral NMOS transistor gate, andgates 58 and 60 correspond to memory array NMOS transistor gates. Alsoshown are field oxide regions 62 between the transistor gates and a wordline 64 (only a portion of which is shown) over one of the field oxideregions. Gates 54, 56, 58 and 60, as well as word line 64, all comprisea gate oxide layer 66, a polysilicon layer 68, a refractory metal layer70, an upper oxide layer 71, and a cap 72, as was described previouslyregarding transistor device 14. Further, each of gates 54, 56, 58, and60, as well as word line 64, comprise opposing lateral sidewalls 63.

[0015] A prior art processing method of forming graded junction regionsfor the circuitry of FIG. 2 is described with reference to FIGS. 3-6.

[0016] Referring to FIG. 3, n-type regions 74 and 76 are implanted intoperipheral and memory NMOS regions 46 and 48 respectively. Regions 74are peripheral NMOS LDD regions implanted operatively adjacentperipheral NMOS gate 56, while regions 76 are memory array source/drainregions implanted operatively adjacent memory array NMOS gates 58 and60. As the memory array source/drain regions 76 are typically implantedat a dopant concentration and depth comparable to the peripheral NMOSLDD regions 74, regions 74 and 76 are typically implanted during acommon implant step.

[0017] Also referring to FIG. 3, p-type LDD regions are implantedoperatively adjacent PMOS gate 54 to form PMOS LDD regions 78.

[0018] After the implant of regions 74, 76, and 78, the polysilicon ofgates 54, 56, 58 and 60 as well as of word line 64 and upper surface 61is oxidized to form the silicon oxide layer 80.

[0019] Referring to FIG. 4, a first masking layer provision step occursas PMOS region 44 and memory array region 48 are covered with a maskinglayer 82, preferably of photoresist. Subsequently, a p-type dopant 84 isimplanted into peripheral NMOS region 46 to form peripheral NMOS haloregions 86 operatively adjacent peripheral NMOS gate 56. Halo regions 86are displaced further from gate 56 than LDD regions 74 as a result ofLDD regions 74 being implanted prior to formation of oxide layer 80 andhalo regions 86 being implanted subsequent to formation of oxide layer80.

[0020] Referring to FIG. 5, masking layer 82 is removed and subsequentlysidewall spacers 88, 90, 92, 94 and 96 are provided adjacent gates 54,56, 58, 60 and word line 64, respectively.

[0021] Referring to FIG. 6, a second masking layer provision step occursas PMOS region 44 and memory array region 48 are again masked, this timewith a masking layer 98, preferably of photoresist. Subsequently, n-typedopant 100 is implanted into peripheral NMOS region 46 to formperipheral NMOS source/drain regions 102 operatively adjacent peripheralNMOS gate 56. Source/drain regions 102 are displaced further from gate56 than graded junction regions 74 and 86 as a result of source/drainregions 102 being implanted subsequent to provision of sidewall spacers90 and graded junction regions 74 and 86 being implanted prior toprovision of sidewall spacers 90.

[0022] The net result of the steps shown in FIGS. 2-6 is to create aperipheral NMOS having source/drain regions 102, halo regions 86, andLDD regions 74, and to further create an array of NMOS memory devicetransistors having source/drain regions 76. Thus, the net result of theprocessing of FIGS. 2-6 is to create a peripheral NMOS transistor device101 and an array of NMOS memory transistor devices 103.

[0023] The memory transistors 103 and peripheral NMOS transistor 101 arenext typically further processed by: (1) deposition of a nitride oroxide cap over transistors 101 and 103 to block borophosphosilicateglass (BPSG) out-diffusion; (2) BPSG deposition over transistors 101 and103; (3) the formation of contact openings to the source/drain regionsof transistors 101 and 103; and (4) the provision of conductive plugswithin the contact openings to form ohmic contacts with the source/drainregions.

[0024] A problem with the processing of FIGS. 3-6 is that the shown twoseparate masking steps (the masking steps of FIGS. 4 and 6) are utilizedbetween the formation of the peripheral NMOS LDD region 74 (shown inFIG. 3) and the implant of source/drain regions 102 (shown in FIG. 6)during the formation of the peripheral NMOS transistor 101. As eachmasking step carries with it a risk of mask misalignment, it would bedesirable to eliminate at least one of the masking steps. Also, andperhaps more importantly, as the cost of forming an integrated circuitincreases as the number of masking steps is increased, it would bedesirable to eliminate at least one of the masking steps.

[0025] Although the above discussion of prior art was limited towardapplications in which the PMOS transistor gate and NMOS transistor gateswere patterned concurrently (a so-called “non-split-poly” process),similar masking steps, and associated desirability of eliminatingmasking steps, occur in applications in which a PMOS transistor gate ispatterned non-concurrently with the NMOS transistor gates (the so-called“split-poly” processes). A prior art split-poly process is describedwith reference to FIGS. 7-12.

[0026] Referring to FIG. 7, a semiconductor wafer fragment 240 isillustrated at a processing step in accordance with the prior art.Fragment 240 comprises a portion of a semiconductor material wafer 42,which is preferably the same type of semiconductor material as discussedpreviously regarding FIGS. 2-6. The shown wafer fragment 240 issubdivided into three defined regions: PMOS region 244 (only a portionof which is shown), peripheral NMOS region 246, and memory array region248 (only a portion of which is shown). Regions 244 and 246 togethercomprise a defined peripheral region 250 (only a portion of which isshown).

[0027] The semiconductor material of wafer 42 within peripheral NMOSregion 246 and memory array region 248 is typically polysilicon lightlydoped with a p-type impurity. The semiconductor material of wafer 42within PMOS region 244 is typically polysilicon comprising a well 252which is lightly doped with an n-type impurity.

[0028] A series of field oxide regions 262 are provided on top of wafer42. Between field oxide regions 262, and over a top surface 261 of wafer42, is provided a gate oxide layer 266. Over gate oxide layers 266 andover field oxide regions 262 is provided a gate layer 253. Gate layer253 typically comprises a polysilicon layer 268, a refractory metallayer 270, an upper oxide layer 271 and a cap 272.

[0029] Referring to FIG. 8, gate layer 253 is patterned over peripheralNMOS and memory array regions 246 and 248, while leaving layer 253unpatterned over PMOS region 244. Accordingly, a series of transistorgates, 256, 258 and 260, are formed over regions 246 and 248 whileleaving an unpatterned gate layer strip 251 over region 244. Alsopatterned is a word line 264 (only a portion of which is shown) over oneof the field oxide regions of memory array region 248.

[0030] Gate 256 corresponds to a peripheral NMOS transistor gate andgates 258 and 260 correspond to memory array NMOS transistor gates. Thegates, as well as word line 264, all comprise a gate oxide layer 266, apolysilicon layer 268, a refractory metal layer 270, an upper oxidelayer 271, and a cap 272; structures which were described previouslyregarding transistor device 14. Also, each of gates 256, 258 and 260, aswell as word line 264, comprise opposing lateral sidewalls 263.

[0031] Referring to FIG. 9, n-type regions 274 and 276 are implantedinto peripheral and memory NMOS regions 246 and 248, respectively.Regions 274 are peripheral NMOS LDD regions implanted operativelyadjacent peripheral NMOS gate 256, while regions 276 are memory arraysource/drain regions implanted operatively adjacent memory array NMOSgates 258 and 260. As the memory array source/drain regions 276 aretypically implanted at a dopant concentration and depth comparable tothe peripheral NMOS LDD regions 274, regions 274 and 276 are typicallyimplanted during a common implant step.

[0032] After the implant of regions 274 and 276, the polysilicon ofgates 256, 258 and 260, word line 264, upper surface 261 and unpatternedgate layer strip 251 is oxidized to form silicon oxide layer 280.

[0033] Referring to FIG. 10, a first masking layer provision step occursas memory array region 248 is covered with a masking layer 282,preferably of photoresist. Subsequently, a p-type dopant 284 isimplanted into peripheral NMOS region 246 to form peripheral NMOS haloregions 286 operatively adjacent peripheral NMOS gate 256. The PMOSregion 244 is typically not covered by masking layer 282, as the caplayer 272 of unpatterned gate layer strip 251 is typically thick enoughto effectively inhibit penetration of dopant 284 into the materialbeneath the cap layer 272.

[0034] Halo regions 286 are displaced further from gate 256 than LDDregions 274 as a result of LDD regions 274 being implanted prior toformation of oxide layer 280 and halo regions 286 being implantedsubsequent to formation of oxide layer 280.

[0035] Referring to FIG. 11, masking layer 282 is removed. Subsequently,sidewall spacers 288, 290, 292, 294 and 296 are provided adjacentunpatterned gate layer strip 251, gates 256, 258 and 260, and word line264, respectively. The sidewall spacers over the memory array region 248will ultimately function to electrically insulate word line 264 from thememory devices encompassing memory transistors 258 and 260. The sidewallspacers over peripheral NMOS region 246, i.e., sidewall spacers 290,will ultimately function to space peripheral NMOS source/drain regionsoutwardly from gate 256 relative the graded junction regions 274 and286, as shown in FIG. 12.

[0036] Referring to FIG. 12, a second masking layer provision stepoccurs as memory array region 248 is again masked, this time with amasking layer 298, preferably of photoresist. Subsequently, n-typedopant 300 is implanted into peripheral NMOS region 246 to formperipheral NMOS source/drain regions 302 operatively adjacent peripheralNMOS gate 256. As alluded to above with reference to FIG. 11,source/drain regions 302 are displaced further from gate 256 than gradedjunction regions 274 and 286 as a result of the use of sidewall spacers290. More specifically, source/drain regions 302 are displaced furtheroutward from gate 256 than regions 274 and 286 because regions 302 wereimplanted subsequent to the provision of the sidewall spacers 290whereas regions 274 and 286 were implanted prior to provision of thesidewall spacers 290.

[0037] The net result of the processing of FIGS. 7-12 is to create aperipheral NMOS transistor device 301, an array of insulated NMOS memorytransistor devices 303 and an insulated word line 307. The peripheralNMOS device 301 further comprising source/drain regions 302, haloregions 286, and LDD regions 274; and the array of NMOS memory devicetransistors 303 further comprising source/drain regions 276.

[0038] The memory transistors 303 and peripheral NMOS transistor 301 arenext typically further processed by: (1) deposition of a silicon nitrideor silicon oxide cap over transistors 301 and 303 to blockborophosphosilicate glass (BPSG) out-diffusion; (2) BPSG deposition overtransistors 301 and 303; (3) the formation of contact openings to thesource/drain regions of transistors 301 and 303; and (4) the provisionof conductive plugs within the contact openings to form ohmic contactswith the source/drain regions. Also, a PMOS transistor would typicallybe provided over PMOS region 244 by patterning unpatterned masking layerstrip 251 to form a transistor gate and then providing source/drainregions, and possibly graded junction regions, operatively adjacent thetransistor gate. The formed PMOS transistor and one or more of the NMOStransistors could be utilized in formation of CMOS circuitry.

[0039] A problem with the prior art processing sequence of FIGS. 7-12 isthat two separate masking layer provision steps are utilized between theformation of the peripheral NMOS LDD region 274 (shown in FIG. 9) andthe implant of source/drain regions 302 (shown in FIG. 12) whichcompletes formation of the peripheral NMOS transistor device 301. Aseach masking layer provision step carries with it a risk of maskmisalignment, it would be desirable to eliminate at least one of thesetwo steps. Also, and perhaps more importantly, as the cost of forming anintegrated circuit increases as the number of masking layer provisionsteps is increased, it would be desirable to eliminate at least one ofthese two steps.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0041]FIG. 1 is a diagrammatic fragmentary sectional view of a prior artsemiconductor wafer fragment illustrating a transistor device known inthe art.

[0042]FIG. 2 is a diagrammatic fragmentary sectional view of asemiconductor wafer fragment at one processing step in accordance with aprior art processing method.

[0043]FIG. 3 is a view of the FIG. 2 wafer shown at a processing stepsubsequent to that shown in FIG. 2.

[0044]FIG. 4 is a view of the FIG. 2 wafer shown at a processing stepsubsequent to that of FIG. 3.

[0045]FIG. 5 is a view of the FIG. 2 wafer shown at a step subsequent tothat of FIG. 4.

[0046]FIG. 6 is a view of the FIG. 2 wafer shown at a step subsequent tothat of FIG. 5.

[0047]FIG. 7 is a diagrammatic fragmentary sectional view of asemiconductor wafer fragment at one processing step in accordance with aprior art processing method.

[0048]FIG. 8 is a view of the FIG. 7 wafer shown at a prior artprocessing step subsequent to that shown in FIG. 7.

[0049]FIG. 9 is a view of the FIG. 7 wafer shown at a prior artprocessing step subsequent to that of FIG. 8.

[0050]FIG. 10 is a view of the FIG. 7 wafer shown at a prior artprocessing step subsequent to that of FIG. 9.

[0051]FIG. 11 is a view of the FIG. 7 wafer shown at a prior artprocessing step subsequent to that of FIG. 10.

[0052]FIG. 12 is a view of the FIG. 7 wafer shown at a prior artprocessing step subsequent to that of FIG. 11.

[0053]FIG. 13 is a view of the FIG. 2 wafer fragment shown at aprocessing step in accordance with one embodiment of the invention,shown at a processing step subsequent to that of FIG. 2.

[0054]FIG. 14 is a view of the FIG. 2 wafer shown at a processing stepsubsequent to that of FIG. 13.

[0055]FIG. 15 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 14.

[0056]FIG. 16 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 15.

[0057]FIG. 17 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 16.

[0058]FIG. 18 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 17.

[0059]FIG. 19 is an isometric view of a semiconductor wafer.

[0060]FIG. 20 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 15 in accordance with a second embodiment ofthe invention.

[0061]FIG. 21 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 17 in accordance with the second embodimentof the invention.

[0062]FIG. 22 is a view of the FIG. 2 wafer fragment shown at aprocessing step in accordance with a third embodiment of the invention.

[0063]FIG. 23 is a view of the FIG. 2 wafer fragment shown at a stepsubsequent to that of FIG. 22.

[0064]FIG. 24 is a view of the FIG. 2 wafer fragment shown at aprocessing step subsequent to that of FIG. 23.

[0065]FIG. 25 is a view of the FIG. 2 wafer fragment shown at aprocessing step subsequent to that of FIG. 24.

[0066]FIG. 26 is a view of the FIG. 7 wafer fragment shown at aprocessing step in accordance with a fourth embodiment of the invention,shown at a processing step subsequent to that of FIG. 8.

[0067]FIG. 27 is a view of the FIG. 7 wafer shown at a processing stepsubsequent to that of FIG. 26.

[0068]FIG. 28 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 27.

[0069]FIG. 29 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 28.

[0070]FIG. 30 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 8 in accordance with a fifthembodiment of the invention.

[0071]FIG. 31 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 29.

[0072]FIG. 32 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 28 in accordance with a sixthembodiment of the invention.

[0073]FIG. 33 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 32.

[0074]FIG. 34 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 33.

[0075]FIG. 35 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 32 in accordance with aseventh embodiment of the invention.

[0076]FIG. 36 is a view of the FIG. 7 wafer shown at a processing stepsubsequent to that of FIG. 35.

[0077]FIG. 37 is a view of the FIG. 7 wafer shown at a processing stepsubsequent to that of FIG. 29 in accordance with an eighth embodiment ofthe invention.

[0078]FIG. 38 is a view of the FIG. 7 wafer fragment shown at aprocessing step subsequent to that of FIG. 37.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0080] In one aspect, the invention is a method for implanting gradedjunction regions into a peripheral NMOS transistor and source/drainregions into a memory array of NMOS transistors, the method comprisingthe following steps:

[0081] providing a semiconductor material wafer;

[0082] defining a memory array region of the wafer;

[0083] defining a PMOS region and a peripheral NMOS region of the wafer;

[0084] providing a PMOS transistor gate over the PMOS region, providinga peripheral NMOS transistor gate over the peripheral NMOS region, andproviding an array of memory NMOS transistor gates over the memory arrayregion, the transistor gates having opposing lateral sidewalls;

[0085] providing sidewall spacers adjacent the sidewalls of thetransistor gates, the sidewall spacers having a lateral thickness andcomprising a sidewall spacer material;

[0086] providing a masking layer over the PMOS region and over thememory array region;

[0087] after providing the masking layer over the PMOS region and thememory array region, and after providing the sidewall spacers adjacentthe peripheral NMOS transistor gate, implanting an n-typeconductivity-enhancing dopant into the semiconductor wafer to formelectrically conductive peripheral NMOS source/drain regions within thesemiconductor material operatively adjacent the peripheral NMOStransistor gate;

[0088] after forming the electrically conductive NMOS source/drainregions, etching the sidewall spacer material adjacent the peripheralNMOS transistor gate to remove only a portion of said spacer materialand to thereby decrease the lateral thickness of the sidewall spacersadjacent the peripheral NMOS transistor gate; and

[0089] after decreasing the lateral thickness of the sidewall spacersadjacent the peripheral NMOS transistor gate, implanting p-typeconductivity-enhancing dopant into the semiconductor material to formhalo regions operatively adjacent the peripheral NMOS source/drainregions.

[0090] In another aspect, the invention is a method for forming gradedjunction regions operatively adjacent a transistor gate, the methodcomprising the following steps:

[0091] providing a semiconductor material wafer;

[0092] providing a transistor gate over the semiconductor materialwafer, the transistor gate having opposing lateral sidewalls;

[0093] providing sidewall spacers adjacent the sidewalls of thetransistor gate, the sidewall spacers having a lateral thickness andcomprising a sidewall spacer material;

[0094] after providing the sidewall spacers, implanting a firstconductivity-enhancing dopant into the semiconductor wafer to formelectrically conductive source/drain regions within the semiconductormaterial operatively adjacent the transistor gate;

[0095] after forming the electrically conductive source/drain regions,etching the sidewall spacer material to remove only a portion of saidspacer material and to thereby decrease the lateral thickness of thesidewall spacers; and

[0096] after decreasing the lateral thickness of the sidewall spacers,implanting a second conductivity-enhancing dopant into the semiconductormaterial to form graded junction regions operatively adjacent thesource/ drain regions.

[0097] In yet another aspect, the invention is a semiconductortransistor device comprising:

[0098] a region of a semiconductor material wafer;

[0099] a transistor gate over a portion of the region of thesemiconductor material wafer, the transistor gate having opposinglateral sidewalls;

[0100] opposing source/drain regions operatively adjacent the transistorgate, each source/drain region having an inner lateral boundary;

[0101] opposing sidewall spacers adjacent the sidewalls of thetransistor gate, each sidewall spacer having an outer lateral edge, thesidewall spacers and source/drain regions being paired such that theouter lateral edges of the sidewall spacers are displaced laterallyinwardly relative to the inner lateral boundaries of the source/drainregions; and

[0102] lateral gaps, the lateral gaps extending from the outer lateraledges of the sidewall spacers to the inner lateral boundaries of thesource/drain regions.

[0103] In yet another aspect, the invention is a method for forminggraded junction regions operatively adjacent a transistor gate of CMOScircuitry, the method comprising the following steps:

[0104] providing a semiconductor material wafer;

[0105] defining a PMOS region and an NMOS region of the wafer;

[0106] providing a gate layer over the PMOS region and over the NMOSregion;

[0107] patterning the gate layer over the NMOS region to form an NMOStransistor gate over the NMOS region while leaving the gate layer overthe PMOS region unpatterned, the NMOS transistor gate having opposinglateral sidewalls;

[0108] providing sidewall spacers adjacent the sidewalls of the NMOStransistor gate, the sidewall spacers having a lateral thickness andcomprising a sidewall spacer material;

[0109] after providing the sidewall spacers, forming electricallyconductive NMOS source/drain regions within the semiconductor materialoperatively adjacent the NMOS transistor gate;

[0110] after forming the electrically conductive NMOS source/drainregions, etching the sidewall spacer material adjacent the NMOStransistor gate to remove only a portion of said spacer material and tothereby decrease the lateral thickness of the sidewall spacers; and

[0111] after decreasing the lateral thickness of the sidewall spacersadjacent the NMOS transistor gate, implanting conductivity-enhancingdopant into the semiconductor material to thereby form NMOS gradedjunction regions operatively adjacent the NMOS source/drain regions.

[0112] More specifically, the invention pertains to semiconductortransistor devices, to methods of forming such transistor devices, andto methods for forming graded junction regions within such devices. Theinvention is thought to have particular pertinence to areas ofintegrated device formation wherein a peripheral NMOS transistor deviceis formed in conjunction with an array of memory NMOS devices. A firstembodiment of the invention is described with reference to FIGS. 13-16.

[0113] Referring first to FIG. 13, a semiconductor wafer fragment 40 isshown at a processing step subsequent to that of the prior art step ofFIG. 2. The semiconductor wafer fragment 40 of FIG. 13 is actuallyidentical to the wafer fragment 40 of FIG. 3, and is generally producedby the prior art methods described above regarding FIG. 3. Accordingly,wafer fragment 40 of FIG. 13 comprises defined PMOS, peripheral NMOS,and memory array regions 44, 46 and 48, as well as a defined peripheralregion 50. Wafer fragment 40 further comprises a polysiliconsemiconductor material wafer 42 above which is provided a PMOStransistor gate 54, a peripheral NMOS transistor gate 56, NMOS memoryarray transistor gates 58 and 60, and a word line 64. The gates and wordline comprise a gate oxide layer 66, a polysilicon layer 68, arefractory metal layer 70, an upper oxide layer 71, and a cap layer 72.Cap layer 72 is preferably silicon nitride, and preferably has avertical thickness “Z” of from about 1500 Angstroms to about 4500Angstroms, with 3000 Angstroms being most preferred.

[0114] The FIG. 13 wafer further comprises peripheral NMOS and PMOS LDDregions 74 and 78, as well as memory NMOS source/drain regions 76. Also,gates 54, 56, 58 and 60 comprise opposing lateral sidewalls 63. Asilicon oxide layer 80 extends along the polysilicon sidewalls of gates54, 56, 58 and 60, as well as along an upper surface 61 of wafer 42.

[0115] Referring to FIG. 14, sidewall spacers 88, 90, 92, 94 and 96 areprovided adjacent sidewalls 63 of transistor gates 54, 56, 58 and 60, aswell as adjacent word line 64. Methods for provision of such sidewallspacers are known to persons of ordinary skill in the art.

[0116] Sidewall spacers 88, 90, 92, 94 and 96 comprise a sidewall spacermaterial and a lateral thickness “X”. As discussed above regarding theprior art FIG. 1, the sidewall spacer material will preferably besilicon nitride, and thickness “X” will preferably be from about 200Angstroms to about 1000 Angstroms as measured at about the level ofrefractory metal layer 70.

[0117] Referring to FIG. 15, a masking layer provision step occurs asPMOS and memory array regions 44 and 48 are covered with a masking layer104, preferably of photoresist. Subsequently, an n-type conductivityenhancing dopant 106 is implanted into semiconductor material wafer 42to form electrically conductive NMOS source/drain regions 108 within thesemiconductor material water. N-type conductivity enhancing dopant 106will preferably comprise arsenic and will preferably be implanted at adose of from about 1×10¹⁵ atoms/cm² to about 4×10¹⁵ atoms/cm² and at anenergy of from about 10 KeV to about 50 KeV.

[0118] Referring to FIG. 16, the thickness “X” of sidewall spacers 90 isdecreased by removing sidewall spacer material from the spacers 90.Preferably; such removal is accomplished with an isotropic etch. Mostpreferably, the isotropic etch is a high pressure reactive ion etchutilizing NF₃, He, and O₂ Also preferably, the thickness “X” will bedecreased by 10 to 90% of its original value. Most preferably, theoriginal value of thickness “X” will be about 700 Angstroms and thethickness will be decreased by about 400 Angstroms or 57% by the etch.However, the sidewall spacer material of sidewalls 90 may also becompletely removed, as discussed in more detail below in regard to FIG.32, to thereby expose the oxide layer 80 adjacent gate 56. It is notedthat, since cap layer 72 is formed from silicon nitride, the etch ofsidewall spacers 90 will also decrease the horizontal thickness “Z” oflayer 72. Preferably, the original thickness “Z” of layer 72 will besubstantially more than the original thickness “X” of spacers 90. Forinstance, if spacers 90 have an original thickness “X” of 700 Angstroms,cap layer 72 will preferably have an original thickness “Z” of about3000 Angstroms so that capping layer 72 is not lost during the etch ofsidewalls 90.

[0119] After the etch of sidewalls 90, a p-type conductivity enhancingdopant 110 is implanted into semiconductor material wafer 42 to formperipheral NMOS halo regions 112. P-type conductivity enhancing dopant110 will preferably comprise boron. Most preferably, p-type dopant 110will be BF₂ and will be implanted at a dose of from about 5×10¹²atoms/cm² to about 5×10¹³ atoms/cm² and at an energy of from about 10KeV to about 100 KeV.

[0120] The process of FIGS. 13-16 forms a peripheral NMOS transistor Bydevice 105 and an array of NMOS memory transistor devices 103.Transistors 105 and 103 are functionally comparable integrated devicesto the devices 101 and 103 formed by the prior art process of FIGS. 2-6,but were formed with one less masking layer provision step. The priorart process of FIGS. 2-6 utilizes two masking layer provision steps,shown at FIGS. 4 and 6, after the provision of the peripheral NMOS LDDregion 74 (shown in FIG. 3), and prior to a last implant of dopant (theimplant of dopant 100) which completes transistors 101 and 103. Incontrast, the process of FIGS. 13-16 utilizes only the one masking layerprovision step, shown at FIG. 15, after the provision of the peripheralNMOS LDD region 74 (shown in FIG. 13), and prior to a last implant ofdopant (the implant of dopant 110) which completes transistors 105 and103. Yet, both processes result in the formation of a peripheral NMOS,either 101 or 105, with source/drain regions, halo regions and LDDregions, as well as in the formation of an array of NMOS memorytransistors 103 with source/drain regions.

[0121] A difference between the transistor device 105 formed by theprocess of FIGS. 13-16 and the prior art transistor devices, such asexemplified by the devices 14 in FIG. 1 and 101 in FIG. 6, is in thelocation of the source/drain regions relative to the sidewall spacers.The sidewall spacers 90 of transistor device 105 have outer lateraledges 91 which are displaced laterally inwardly relative to an innerlateral boundary 107 of source/drain regions 108. Thus, a lateral gap 93exists between the outer lateral edge 91 of sidewall spacer 90 and theinner lateral boundary 107 of source/drain regions 108. No such lateralgap exists in prior art transistor devices 14 and 101.

[0122] The length of lateral gap 93 will be approximately equal to theamount by which the lateral thickness “X” of sidewall spacers 90 isdecreased subsequent to the formation of source/drain regions 108. Forinstance, in the most preferable aspect of the invention discussed abovewith reference to FIG. 16, the lateral thickness “X” is decreased byabout 400 Angstroms after formation of source/drain regions 108. In sucha most preferable aspect of the invention, the length of the lateral gap93 in the resulting transistor device 105 will also be about 400Angstroms. Preferably, the length of lateral gap 93 will be from about150 Angstroms to about 600 Angstroms.

[0123] As shown in FIG. 16, the lateral gap 93 essentially provides aslit or pocket for implanting graded junction regions 112 inwardlyadjacent to source/drain regions 108. Thus, in the shown preferredaspect of the invention, the lateral gap 93 within wafer 42 comprises agraded junction region 112 which is inwardly adjacent source/drainregions 108.

[0124] The process of the present invention may be further utilized incompleting formation of a PMOS transistor over PMOS region 44 asdescribed with reference to FIGS. 17 and 18.

[0125] Referring to FIG. 17, masking layer 104 is stripped from overPMOS region 44 and a masking layer 114 is provided over peripheral NMOSregion 46. Next, a p-type conductivity enhancing dopant 116 is implantedinto the semiconductor material wafer 42 to form PMOS source/drainregions 118 operatively adjacent PMOS gate 54. P-type conductivityenhancing dopant 116 preferably comprises boron. Most preferably, p-typedopant 116 comprises BF₂ and is implanted at a dose of from about 1×10¹⁵atoms/cm² to about 5×10¹⁵ atoms/cm² and at an energy of from about 10KeV to about 40 KeV.

[0126] Referring to FIG. 18, the lateral thickness “X” of spacers 88 isreduced by removing spacer material. Preferably, this removal of spacermaterial comprises the same preferable conditions described above withreference to FIG. 16.

[0127] After decreasing the lateral thickness “X” of sidewall spacers88, n-type dopant 120 is implanted into wafer 42 to form PMOS haloregions 122. The n-type dopant 120 preferably comprises phosphorus andis preferably implanted at a dose of from about 1×10¹² atoms/cm² toabout 5×10¹³ atoms/cm² and at implant energy of from about 30 KeV toabout 70 KeV.

[0128] The formation of halo regions 122 completes formation of a PMOStransistor 124 comprising PMOS gate 54, source/drain regions 118, LDDregions 78, and halo regions 122.

[0129] In combination, processing steps 13-18 of the present inventionproduce the PMOS transistor device 124, the peripheral NMOS transistordevice 105, and the NMOS memory transistor devices 103. An alternateembodiment of the present invention is described with reference to FIGS.19, 20 and 21.

[0130] Referring to FIG. 19, semiconductor wafer material 42, whenviewed from a distance, has an overall planar configuration whichestablishes a virtual planar top surface 126 and an axis “Y” normal tovirtual planar top surface 126. It is to be understood that virtualplanar top surface 126 is an imaginary surface. The virtual surface 126is defined as the apparently flat surface of a semiconductor wafermaterial which appears when the wafer is viewed from a distance. Thus,virtual surface 126 exists regardless of whether the actual top surface61 (shown, for example, in FIG. 13) of semiconductor material wafer 42contains crevasses, protrusions, or devices, such as would result fromprior semiconductor processing steps.

[0131] Referring to FIG. 20, wafer fragment 40 is shown at a processingstep subsequent to that of FIG. 15. In FIG. 20, the lateral thickness“X” of opposing lateral sidewalls 90 has been decreased in a processsimilar to that described with reference to FIG. 16. Also, in FIG. 20the p-type dopant 110 is implanted into semiconductor material wafer 42to form NMOS halo regions in a manner similar to that described withreference to FIG. 16. However, the embodiment of FIG. 20 differs fromthat of FIG. 16 in that dopant 110 is implanted at an angle other thanparallel to the axis “Y” normal to the virtual planar top surface 126(shown in FIG. 19) of semiconductor wafer material 42. Due to the angledimplant of dopant 110, the resulting peripheral NMOS halo implantregions 128 are toed slightly inward and may actually penetrate beneathsilicon oxide layer 80 adjacent gate sidewalls 63, and may evenpenetrate beneath the gate 56.

[0132] For the angled implant of FIG. 20, p-type dopant 110 ispreferably BF₂ and is preferably implanted at a dose of from about1×10¹² atoms/cm² to about 1×10¹³ atoms/cm² and at an energy of fromabout 20 KeV to about 120 KeV.

[0133] Referring to FIG. 21, wafer fragment 40 is shown at a processingstep subsequent to that of FIG. 17. Sidewall spacers 88 have beenreduced in lateral thickness “X”, preferably by the methods discussedabove with reference to FIG. 18. The difference between FIG. 21 and FIG.18 is that in FIG. 21 the n-type conductivity enhancing dopant 120 isimplanted at an angle other than parallel to the axis “Y” normal to thevirtual planar surface 126 (shown in FIG. 19) of semiconductor materialwafer 42 to form PMOS halo implant regions 130. Due to the angledimplant of dopant 120, halo implants 130 are toed inward towardtransistor gate 54 and may in fact penetrate beneath oxide layer 80adjacent sidewalls 63 of gate 54, and may even penetrate beneath gate 54itself.

[0134] For the angled implant of FIG. 21, dopant 120 is preferablyphosphorus and is preferably implanted at a dose of from about 1×10¹²atoms/cm² to about 1×10¹³ atoms/cm² and at an energy of from about 20KeV to about 120 KeV.

[0135] A further embodiment of the invention is described with referenceto FIGS. 22-25.

[0136] Referring to FIG. 22, a semiconductor wafer fragment 40 is shownsubsequent to the processing step of FIG. 2. Silicon oxide layers 80 areformed and sidewall spacers 88, 90, 92, 94 and 96 are provided adjacentgates 54, 56, 58 and 60, as well as adjacent word line 64.

[0137] Referring to FIG. 23, PMOS source/drain regions 134 and NMOSsource/drain regions 136 are provided adjacent PMOS gate 54 andperipheral NMOS gate 56, respectively. Methods for forming source/drainregions 134 and 136 are known to persons of ordinary skill in the art.Generally, such methods would comprise: (1) masking memory array region48 and PMOS region 44 while implanting an n-type dopant into region 46to form source/drain regions 136; (2) stripping the masking layer fromover the NMOS region 46; (3) masking NMOS region 46 and memory arrayregion 48 while implanting a p-type dopant into PMOS region 44 to formsource/drain regions 134; and (4) stripping the masking layer from overthe PMOS region 44.

[0138] Referring to FIG. 24, the lateral thickness “X” of sidewallspacers 88, 90, 92, 94 and 96 has been reduced, preferably by an etchingstep such as the etching step described above with reference to FIG. 16.Subsequent to the reduction of lateral thickness “X”, an n-typeconductivity enhancing dopant 138 is implanted into semiconductormaterial wafer 42 to form PMOS halo regions 140, peripheral NMOS LDDregions 142, and memory array source/drain regions 144. In the shownembodiment, dopant 138 is implanted at an angle other than parallel tothe axis “Y” normal to virtual planar surface 126 of semiconductor wafermaterial 42 (shown in FIG. 19). Such an angled implant of dopant 138 mayimprove the penetration of dopant 138 beneath sidewall spacers 88, 90,92 and 94. However, in a less preferred aspect of the invention, dopant138 could also be implanted at an angle parallel to axis “Y”. Preferablydopant 138 is phosphorus and is implanted under either the conditionsdescribed above with reference to FIG. 18, or under the conditionsdescribed with reference to FIG. 21.

[0139] Referring to FIG. 25, a masking layer 132, preferably ofphotoresist, is provided over memory array region 48. Subsequently ap-type dopant 142 is implanted into PMOS region 44 and peripheral NMOSregion 46 to form PMOS LDD regions 145 operatively adjacent PMOS gate 54and to form peripheral NMOS halo regions 146 operatively adjacent NMOSgate 56. For reasons similar to those discussed above regarding FIG. 24,dopant 142 is preferably implanted at an angle to axis “Y” as shown.However, in a less preferred aspect of the invention, the dopant mayalso be implanted parallel to axis “Y”. Preferably dopant 142 is BF₂ andis implanted under the either the conditions described above withreference to FIG. 17 or under the conditions described with reference toFIG. 20.

[0140] The embodiment of the invention shown in FIGS. 22-25 thus forms aPMOS transistor 148, a NMOS transistor 150, and memory array transistors151 and 152.

[0141] The PMOS transistors, peripheral NMOS transistors, and memoryarray transistors formed by any of the embodiments described above maybe further processed by: (1) deposition of a nitride or oxide cap overthe transistors to block borophosphosilicate glass (BPSG) out-diffusion;(2) BPSG deposition over the transistors; (3) the formation of contactopenings to the source/drain regions of the transistors; and (4) theprovision of conductive plugs within the contact openings to form ohmiccontacts with the source/drain regions.

[0142] It is to be understood that the invention is not to be limited bythe embodiments shown in the drawings. For instance, silicon oxide layer80 is shown as formed prior to the peripheral NMOS LDD regions and thememory array source/drain regions throughout the illustratedembodiments. However, silicon oxide layer 80 would not necessarily haveto be formed at all, and would also not necessarily need to be formedprior to formation of any of the shown graded junction regions orsource/drain regions.

[0143] Whereas the above-described embodiments were primarily directedtoward application of the present invention to non-split-poly processes,the following embodiments, embodiments 4-8, are directed primarilytoward application of the present invention to split-poly processes. Thefourth embodiment of the invention is described with reference to FIGS.26-29.

[0144] Referring first to FIG. 26, a semiconductor wafer fragment 240 isshown at a processing step subsequent to that of the prior art step ofFIG. 8. The semiconductor wafer fragment 240 of FIG. 26 is actuallyidentical to the wafer fragment 240 of FIG. 9, and is generally producedby the prior art methods described above regarding FIG. 9. Accordingly,wafer fragment 240 of FIG. 26 comprises defined PMOS, peripheral NMOS,and memory array regions 244, 246 and 248, as well as a definedperipheral region 250. Wafer fragment 240 further comprises apolysilicon semiconductor material wafer 42 above which is provided anunpatterned gate layer strip 251, a peripheral NMOS transistor gate 256,NMOS memory array transistor gates 258 and 260, and a word line 264. Themasking layer strip, gates and word line comprise a polysilicon layer268, a refractory metal layer 270, an upper oxide layer 271, and a caplayer 272. Cap layer 272 is preferably silicon nitride, and preferablyhas a vertical thickness “Z” of from about 1500 Angstroms to about 4500Angstroms, with 3000 Angstroms being most preferred. The gates and wordline further comprise a gate oxide layer 266.

[0145] The FIG. 26 wafer further comprises peripheral NMOS LDD region274, and memory NMOS source/drain regions 276. Also, gates 256, 258 and260, as well as word line 264 comprise opposing lateral sidewalls 263. Asilicon oxide layer 280 extends along the polysilicon sidewalls ofunpatterned gate layer strip 251, gates 256, 258 and 260, word line 264,and along an upper surface 261 of wafer 42.

[0146] Referring to FIG. 27, sidewall spacers 288, 290, 292, 294 and 296are provided adjacent sidewalls 263 of transistor gates 256, 258 and260, as well as adjacent masking layer strip 251 and word line 264.Methods for provision of such sidewall spacers are known to persons ofordinary skill in the art.

[0147] Sidewall spacers 288, 290, 292, 294 and 296 comprise a sidewallspacer material and a lateral thickness “X”. As discussed aboveregarding the prior art FIG. 1, the sidewall spacer material willpreferably be silicon nitride, and thickness “X” will preferably be fromabout 200 Angstroms to about 1000 Angstroms, as measured at about thelevel of refractory metal layer 270.

[0148] Referring to FIG. 28, a masking layer provision step occurs asmemory array region 248 is covered with a masking layer 304. Preferably,masking layer 304 is photoresist. Subsequently, an n-type conductivityenhancing dopant 306 is implanted into semiconductor material wafer 42to form electrically conductive NMOS source/drain regions 308 within thesemiconductor material water. N-type conductivity enhancing dopant 306will preferably comprise arsenic and will preferably be implanted at adose of from about 1×10¹⁵ atoms/cm² to about 4×10¹⁵ atoms/cm² and at anenergy of from about 10 KeV to about 50 KeV.

[0149] Referring to FIG. 29, the thickness “X” of sidewall spacers 290is decreased by removing sidewall spacer material from the spacers 290.The thickness “X” may even be reduced to zero, i.e., the spacers 290entirely removed, as discussed below with reference to FIG. 32.

[0150] Preferably, the removal of the sidewall spacer material isaccomplished with an isotropic etch. Most preferably, the isotropic etchcomprises a high pressure reactive ion etch utilizing NF₃, He, and O₂ Itis noted that, since cap layer 272 is formed from silicon nitride, theetch of sidewall spacers 290 will also decrease the horizontal thickness“Z” of layer 272.

[0151] As sidewall spacer 288 and cap layer 272 of masking strip 251 areexposed to the above-described spacer etch, the thickness of sidewallspacers 288 and cap layer 272 of masking strip 251 are also reduced bythe etch.

[0152] After the etch of sidewalls 290, a p-type conductivity enhancingdopant 310 is implanted into semiconductor material wafer 42 to formperipheral NMOS halo regions 312. P-type conductivity enhancing dopant310 will preferably comprise boron. Most preferably, p-type dopant 310will be BF₂ and will be implanted at a dose of from about 5×10¹²atoms/cm² to about 5×10¹³ atoms/cm² and at an energy of from about 10KeV to about 100 KeV.

[0153] The process of FIGS. 26-29 forms a peripheral NMOS transistordevice 305, an array of NMOS memory transistor devices 303 and aninsulated word line 307. Transistor devices 305 and 303 are functionallycomparable to the devices 301 and 303 formed by the prior art process ofFIGS. 7-12, but were formed with one less masking layer provision step.

[0154] The prior art process of FIGS. 7-12 utilizes the two maskinglayer provision steps, shown at FIGS. 10 and 12, after provision of thetransistor gates 256, 258 and 260, and prior to the last implant ofdopant (the implant of dopant 300) to complete transistor devices 301and 303.

[0155] In contrast, the process of FIGS. 26-29 utilizes only the onemasking layer provision step, shown at FIG. 28, after the provision ofthe transistor gates and prior to the last implant of dopant (theimplant of dopant 310) to complete transistor devices 303 and 305.

[0156] Yet, both the prior art process of FIGS. 7-12 and the process ofthe present invention at FIGS. 26-29 form a peripheral NMOS, either 301or 305, with source/drain regions, halo regions and LDD regions. Bothprocesses also form of an array of NMOS memory transistors 303 withsource/drain regions.

[0157] A difference between the transistor device 305 formed by theprocess of FIGS. 26-29 and the prior art transistor device 301 formed bythe process of FIGS. 7-12, is in the location of the source/drainregions relative to the sidewall spacers. The sidewall spacers 290 oftransistor device 305 have outer lateral edges 291 which are displacedlaterally inwardly, i.e., closer to gate 256, relative to an innerlateral boundary 307 of source/drain regions 308. Thus, a lateral gap293 exists between the outer lateral edge 291 of sidewall spacer 290 andthe inner lateral boundary 307 of source/drain regions 308. No suchlateral gap exists in prior art transistor device 301.

[0158] The length of lateral gap 293 is approximately equal to theamount by which the lateral thickness “X” of sidewall spacers 290 isdecreased subsequent to the formation of source/drain regions 308. Forinstance, if the lateral thickness “X” is decreased by about 400Angstroms after formation of source/drain regions 308, the length of thelateral gap 93 in the resulting transistor device 305 is also about 400Angstroms. Preferably, the thickness “X” is reduced such that the lengthof lateral gap 293 will be from about 200 Angstroms to about 600Angstroms.

[0159] As shown in FIG. 29, the lateral gap 293 essentially provides aslit or pocket for implanting graded junction regions 312 inwardlyadjacent to source/drain regions 308, relative to gate 256. Thus, in theshown preferred aspect of the invention, the lateral gap 293 withinwafer 42 comprises a graded junction region 312 which is inwardlyadjacent source/drain regions 308.

[0160] A fifth embodiment of the present invention is described withreference to FIG. 30. In FIG. 30, wafer fragment 240 is shown at aprocessing step subsequent to that of FIG. 28. In FIG. 30, the lateralthickness “X” of opposing lateral sidewalls 290 has been decreased in aprocess similar to that described with reference to FIG. 28. Also, inFIG. 30 the p-type dopant 310 is implanted into semiconductor materialwafer 42 to form NMOS halo regions in a manner similar to that describedwith reference to FIG. 29. However, the embodiment of FIG. 30 differsfrom that of FIG. 29 in that dopant 310 is implanted at an angle otherthan parallel to the axis “Y” normal to the virtual planar top surface126 (shown in FIG. 19) of semiconductor wafer material 42. Due to theangled implant of dopant 310, the resulting peripheral NMOS halo implantregions 328 are toed slightly inward and may actually penetrate beneathsilicon oxide layer 280 adjacent gate sidewalls 263, and may evenpenetrate beneath the gate 256.

[0161] For the angled implant of FIG. 30, p-type dopant 310 ispreferably BF₂ and is preferably implanted at a dose of from about1×10¹² atoms/cm² to about 1×10¹² atoms/cm² and at an energy of fromabout 20 KeV to about 120 KeV.

[0162] After the formation of peripheral NMOS transistor device 305 andmemory array transistor devices 303, a PMOS transistor device may beformed over PMOS region 244 as described with reference to FIG. 31.Referring to FIG. 31, wafer fragment 240 is shown at a processing stepsubsequent to that of FIG. 29. A masking layer 314, preferably ofphotoresist, is provided over peripheral NMOS region 246. Subsequently,a PMOS gate 330 is patterned from strip 251 (shown in FIG. 29) andthereafter oxide layers 332 and sidewall spacers 334 are providedadjacent the PMOS gate 330. Also, source/drain regions 336, halo regions338 and LDD regions 340 are provided operatively adjacent gate 330, toform the shown PMOS transistor device 342. Methods for forming the showndevice 342 are known to persons of ordinary skill in the art.

[0163] The wafer fragment 240 may be further processed by: (1) strippingmasking layers 304 and 314 from over peripheral NMOS region 246 andmemory array region 248; (2) deposition of a silicon nitride or siliconoxide cap over transistors 303, 305 and 342 to block borophosphosilicateglass (BPSG) out-diffusion; (3) BPSG deposition over transistors 303,305 and 342; (4) the formation of contact openings to the source/drainregions of transistors 303, 305 and 342; and (5) the provision ofconductive plugs within the contact openings to form ohmic contacts withthe source/drain regions.

[0164] A sixth embodiment of the invention is described with referenceto FIGS. 32-36.

[0165] Referring to FIG. 32, a semiconductor wafer fragment 240 is shownsubsequent to the processing step of FIG. 28. Sidewall spacers 288 and290 have been removed from adjacent unpatterned gate layer strip 251 andgate 256. The sidewall spacers are preferably removed with the etchingprocess which is preferably selective for silicon nitride relative tosilicon oxide. As described above, sidewalls 288 and 290, as well as caplayer 272, are preferably formed of silicon nitride. Accordingly, in thepreferred process shown, spacers 288 and 290, as well as the cappinglayer 272 over PMOS region 244 and peripheral NMOS region 246, areselectively removed with the preferable etch process, leaving oxidelayers 271 and 280 exposed.

[0166] Subsequent to the nitride etch, p-type dopant 310 is implanted toform halo regions 312 operatively adjacent peripheral NMOS gate 256.Preferably, dopant 310 is implanted according to the preferable processdescribed above with reference to FIG. 29.

[0167] The exposed oxide layer 280 adjacent sidewalls 263 of gate 256functions to displace halo implants 312 laterally outward from gate 256.Accordingly, as a result of regions 312 being implanted after oxidelayer 280 is formed and regions 274 being implanted prior to oxide layer280 being formed, the most inward portions of halo regions 312 arespaced laterally outward from gate 256 relative to the most inwardportions of LDD regions 274.

[0168] An advantage of the process shown in FIG. 32 relative to theprocess of FIG. 29 is that the FIG. 32 process results in the formationof an insulated word line 307, and yet also results in the formation ofa peripheral NMOS transistor device 309 lacking an insulating layer overthe oxide layer 271. This is an advantage because it is desirable tohave a thick insulating layer surrounding word line 307 so as to avoidshorts between adjacent storage nodes and word line 307, and yet it isalso desirable to have little or no insulating layer over the oxidelayer 271 of the peripheral NMOS transistor device during subsequentprocessing steps. Such an insulating layer complicates later processesforming contact to the refractory metal layer 272. The peripheral NMOSactive area may, in fact, be severely damaged when a thick insulatinglayer on top of the peripheral NMOS gate is cleared during such contactforming steps.

[0169] Referring to FIG. 33, a masking layer 350, preferably ofphotoresist, is provided over peripheral NMOS region 246. Subsequently,a PMOS transistor gate 331 is patterned from gate layer strip 251. Gate331 comprises a gate oxide layer 266, a polysilicon layer 268, arefractory metal layer 270 and an upper oxide layer 271. The gate 331also comprises a pair of opposing lateral sidewalls 263.

[0170] After PMOS gate 331 is patterned, an overhanging mask 352,preferably of photoresist, is provided over the gate. Overhanging mask352 extends laterally outward beyond the opposing lateral sidewalls 263of gate 331. After provision of mask 352, a p-type dopant 354 isimplanted into PMOS region 244 of wafer 42 to form PMOS source/drainregions 356. PMOS source/drain regions 356 are offset from gate 331 byabout the overhang of overhanging mask 352. P-type dopant 354 ispreferably BF₂ and is preferably implanted at a dose of from about1×10¹⁵ atoms/cm² to about 5×10¹⁵ atoms/cm² and at an energy of fromabout 10 KeV to about 40 KeV.

[0171] Referring to FIG. 34, a dopant 358 is implanted an angle otherthan parallel to the axis “Y” normal to virtual planar surface 126 ofsemiconductor wafer material 42 (shown in FIG. 19). Such an angledimplant of dopant 358 provides graded junction regions 360 operativelyadjacent PMOS transistor gate 331 and inwardly adjacent of source/drainregions 356. Dopant 358 may be either an n-type conductivity enhancingdopant, such as phosphorus, or a p-type conductivity enhancing dopant,such as BF₂, depending on whether LDD regions or halo regions are to beformed. Also, multiple angled implants may be performed such that bothLDD regions and graded junction regions are formed. The methods forperforming such angled implants are known to persons of ordinary skillin the art. In alternative methods of the invention, which are notshown, dopant 358 may be provided at an angle which is parallel to axis“Y” and then diffused to form graded junction regions 360.

[0172] Referring to FIGS. 35 and 36, a seventh embodiment of theinvention, comprising an alternate method for forming PMOS source/drainregions and graded junction regions subsequent to the step of FIG. 32,is shown. Referring to FIG. 35, a non-overhanging masking layer 364,preferably of photoresist, is provided on top of PMOS transistor gate331. After provision of masking layer 364, p-type dopant 354 isimplanted, preferably as described above with reference to FIG. 33, toform PMOS source/drain regions 366 operatively adjacent PMOS transistorgate 331. Thereafter, as shown in FIG. 36, second dopant 358 isimplanted to form graded junction regions 368. As described above withrelation to FIG. 34, dopant 358 may be either an n-type dopant or ap-type dopant depending on whether the graded junctions to be formed areto be LDD regions or halo regions. Also, multiple implants of dopant maybe provided to form both LDD regions and halo regions operativelyadjacent PMOS transistor gate 331.

[0173]FIGS. 37 and 38 illustrate an eighth embodiment of the inventionwhich may follow either FIG. 29 or FIG. 30. In the shown process, theembodiment follows FIG. 30 as indicated by the toed inward halo regions328.

[0174] The embodiment of FIGS. 37 and 38 has the advantage discussedabove in relation to FIG. 32 that both an insulated word line 307 (shownin FIG. 38) is formed, and also a peripheral NMOS transistor device 380(shown in FIG. 38) lacking an insulating layer over the oxide layer 271is formed. The embodiment of FIGS. 37 and 38 has the further advantagethat it produces sidewalls 290 with flat top surfaces 386 (shown in FIG.38).

[0175] Referring to FIG. 37, a masking layer 370 is provided over PMOSregion 244 and peripheral NMOS region 246. As shown, masking layer 370is preferably thinner than the masking layer 304 provided over memoryarray region 248.

[0176] Referring to FIG. 38, masking layers 304 and 370 are etched backsuch that masking layer 370 is about level with the top of oxide layer271 of transistor gate 254. Also, the etching conditions are preferablysuch that sidewall spacers 290 and capping layer 272 are etched.Accordingly, a peripheral PMOS transistor device 380 is formed havingsidewall spacers 290 with flat top surfaces 386 and having an exposedoxide layer 271.

[0177] Subsequent to the process of FIGS. 37 and 38, a PMOS transistordevice may be formed over region 244. Such PMOS transistor deviceformation may be done, for example, by the procedures described abovewith reference to FIGS. 31-36.

[0178] It is to be understood that the invention is not to be limited bythe embodiments shown in the drawings. For instance, silicon oxide layer280 is shown as formed prior to the peripheral NMOS LDD regions and thememory array source/drain regions throughout the illustratedembodiments. However, silicon oxide layer 280 would not necessarily haveto be formed at all, and would also not necessarily need to be formedprior to formation of any of the shown graded junction regions orsource/drain regions. Also, although the methods shown in FIGS. 27, 28,35 and 36 indicate that source/drain regions are formed prior to gradedjunction regions, the procedures could be reversed such that the gradedjunction regions are formed prior to the source/drain regions. Also, theprocedures could be modified such that graded junction regions areformed both prior to and subsequent to the formation of source/drainregions in applications in which more than one graded junction regionimplant is performed.

[0179] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method for forming graded junction regions operatively adjacent atransistor gate of CMOS circuitry, the method comprising the followingsteps: providing a semiconductor material wafer; defining a PMOS regionand an NMOS region of the wafer; providing a PMOS transistor gate overthe PMOS region and providing an NMOS transistor gate over the NMOSregion, the transistor gates having opposing lateral sidewalls;providing sidewall spacers adjacent the sidewalls of the transistorgates, the sidewall spacers having a lateral thickness and comprising asidewall spacer material; providing a masking layer over the PMOSregion; after providing the masking layer over the PMOS region, andafter providing the sidewall spacers adjacent the NMOS transistor gate,implanting an n-type conductivity-enhancing dopant into thesemiconductor wafer to form electrically conductive NMOS source/drainregions within the semiconductor material operatively adjacent the NMOStransistor gate; after forming the electrically conductive NMOSsource/drain regions, etching the sidewall spacer material adjacent theNMOS transistor gate to remove only a portion of said spacer materialand to thereby decrease the lateral thickness of the sidewall spacersadjacent the NMOS transistor gate; and after decreasing the lateralthickness of the sidewall spacers adjacent the NMOS transistor gate,implanting a p-type conductivity-enhancing dopant into the semiconductormaterial to form halo regions operatively adjacent the NMOS source/drainregions.
 2. The method of claim 1 further comprising, after providingtransistor gates over the PMOS region and NMOS region, and prior toproviding sidewall spacers adjacent the sidewalls of the transistorgates, forming NMOS LDD regions operatively adjacent the NMOS transistorgate.
 3. The method of claim 1 further comprising: after forming theelectrically conductive NMOS source/drain regions, and prior to etchingthe sidewall spacer material adjacent the NMOS transistor gate,stripping the masking layer from over the PMOS region; etching thesidewall spacer material adjacent the PMOS transistor gate to decreasethe lateral thickness of the sidewall spacers adjacent the PMOStransistor gate; and after decreasing the lateral thickness of thesidewall spacers adjacent the NMOS transistor gate and the PMOStransistor gate, blanket implanting the p-type conductivity-enhancingdopant into the semiconductor material of both the PMOS region and theNMOS region to form halo regions operatively adjacent the NMOStransistor gate and to form PMOS LDD regions operatively adjacent thePMOS transistor gate.
 4. The method of claim 3 further comprising, priorto decreasing the lateral thickness of the sidewall spacers adjacent thePMOS transistor gate and subsequent to stripping the masking layer fromover the PMOS region, forming electrically conductive PMOS source/drainregions within the semiconductor material operatively adjacent the PMOStransistor gate.
 5. The method of claim 1 further comprising, prior toproviding the masking layer over the PMOS region, forming PMOS LDDregions operatively adjacent the PMOS transistor gate.
 6. The method ofclaim 1 wherein the semiconductor material wafer comprises an overallplanar global configuration, the planar global configurationestablishing a virtual planar top surface and an axis normal to thevirtual planar top surface, and wherein the p-typeconductivity-enhancing dopant is implanted at an angle other thanparallel to the axis normal to the virtual planar top surface.
 7. Themethod of claim 1 further comprising: prior to providing the maskinglayer over the PMOS region, forming PMOS LDD regions operativelyadjacent the PMOS transistor gate; after forming the electricallyconductive NMOS source/drain regions, and prior to etching the sidewallspacer material adjacent the NMOS transistor gate, stripping the maskinglayer from over the PMOS region; etching the sidewall spacer materialadjacent the PMOS transistor gate to decrease the lateral thickness ofthe sidewall spacers adjacent in the PMOS transistor gate; and afterdecreasing the lateral thickness of the sidewall spacers adjacent theNMOS transistor gate and the PMOS transistor gate, blanket implantingthe p-type conductivity-enhancing dopant into the semiconductor materialof both the PMOS region and the NMOS region to form halo regionsoperatively adjacent the NMOS transistor gate and to enhance theconductivity of the PMOS LDD regions.
 8. The method of claim 1 whereinthe semiconductor material wafer comprises an overall planar globalconfiguration, the planar global configuration establishing a virtualplanar top surface and an axis normal to the virtual planar top surface,and further comprising: after forming the electrically conductive NMOSsource/drain regions, and prior to etching the sidewall spacer materialadjacent the NMOS transistor gate, stripping the masking layer from overthe PMOS region; etching the sidewall spacer material adjacent the PMOStransistor gate to remove only a portion of said spacer material and tothereby decrease the lateral thickness of the sidewall spacers adjacentthe PMOS transistor gate; and after decreasing the lateral thickness ofthe sidewall spacers adjacent the NMOS transistor gate and the PMOStransistor gate, blanket implanting the p-type conductivity-enhancingdopant at an angle other than parallel to the axis normal to the virtualplanar top surface to form NMOS halo regions operatively adjacent theNMOS transistor gate and to form PMOS LDD regions operatively adjacentthe PMOS transistor gate.
 9. The method of claim 1 wherein the portionof spacer material removed from the sidewall spacers constitutes no morethan about 90% of the lateral thickness of the sidewall spacers adjacentthe NMOS transistor gate.
 10. The method of claim 1 wherein thesidewalls of the transistor gates comprise polysilicon, the methodfurther comprising: prior to providing sidewall spacers adjacent thesidewalls, oxidizing the polysilicon of the sidewalls.
 11. The method ofclaim 10 further comprising, prior to providing sidewall spacersadjacent the sidewalls of the NMOS transistor gate, forming NMOS LDDregions operatively adjacent the NMOS transistor gate.
 12. CMOScircuitry comprising at least one transistor formed by the method ofclaim
 1. 13. A method for forming graded junction regions operativelyadjacent a transistor gate, the method comprising the following steps:providing a semiconductor material wafer; providing a transistor gateover the semiconductor material wafer, the transistor gate havingopposing lateral sidewalls; providing sidewall spacers adjacent thesidewalls of the transistor gate, the sidewall spacers having a lateralthickness and comprising a sidewall spacer material; after providing thesidewall spacers, implanting a first conductivity-enhancing dopant intothe semiconductor wafer to form electrically conductive source/drainregions within the semiconductor material operatively adjacent thetransistor gate; after forming the electrically conductive source/drainregions, etching the sidewall spacer material to remove only a portionof said spacer material and to thereby decrease the lateral thickness ofthe sidewall spacers; and after decreasing the lateral thickness of thesidewall spacers, implanting a second conductivity-enhancing dopant intothe semiconductor material to form graded junction regions operativelyadjacent the source/drain regions.
 14. The method of claim 13 whereinthe semiconductor material wafer comprises an overall planar globalconfiguration, the planar global configuration establishing a virtualplanar top surface and an axis normal to the virtual planar top surface,and wherein the second conductivity-enhancing dopant is implanted at anangle other than parallel to the axis normal to the virtual planar topsurface.
 15. The method of claim 13 wherein the transistor is a PMOStransistor, the second conductivity-enhancing dopant is a p-type dopant,and the implant of the second conductivity-enhancing dopant forms LDDregions operatively adjacent the PMOS source/drain regions.
 16. Themethod of claim 13 wherein the transistor is a PMOS transistor, thesecond conductivity-enhancing dopant is an n-type dopant, and theimplant of the second conductivity-enhancing dopant forms halo regionsoperatively adjacent the PMOS source/drain regions.
 17. The method ofclaim 16 wherein the second conductivity-enhancing dopant comprisesphosphorus.
 18. The method of claim 13 wherein the transistor is an NMOStransistor, the second conductivity-enhancing dopant is a p-type dopant,and the implant of the second conductivity-enhancing dopant forms haloregions operatively adjacent the NMOS source/drain regions.
 19. Themethod of claim 18 wherein the second conductivity-enhancing dopantcomprises boron.
 20. The method of claim 13 wherein the transistor is anNMOS transistor, the second conductivity-enhancing dopant is a n-typedopant, and the implant of the second conductivity-enhancing dopantforms LDD regions operatively adjacent the NMOS source/drain regions.21. A transistor formed by the method of claim
 13. 22. A method forimplanting graded junction regions into a peripheral NMOS transistor andsource/drain regions into a memory array of NMOS transistors, the methodcomprising the following steps: providing a semiconductor materialwafer; defining a memory array region of the wafer; defining a PMOSregion and a peripheral NMOS region of the wafer; providing a PMOStransistor gate over the PMOS region, providing a peripheral NMOStransistor gate over the peripheral NMOS region, and providing an arrayof memory NMOS transistor gates over the memory array region, thetransistor gates having opposing lateral sidewalls; providing sidewallspacers adjacent the sidewalls of the transistor gates, the sidewallspacers having a lateral thickness and comprising a sidewall spacermaterial; providing a masking layer over the PMOS region and over thememory array region; after providing the masking layer over the PMOSregion and the memory array region, and after providing the sidewallspacers adjacent the peripheral NMOS transistor gate, implanting ann-type conductivity-enhancing dopant into the semiconductor wafer toform electrically conductive peripheral NMOS source/drain regions withinthe semiconductor material operatively adjacent the peripheral NMOStransistor gate; after forming the electrically conductive NMOSsource/drain regions, etching the sidewall spacer material adjacent theperipheral NMOS transistor gate to remove only a portion of said spacermaterial and to thereby decrease the lateral thickness of the sidewallspacers adjacent the peripheral NMOS transistor gate; and afterdecreasing the lateral thickness of the sidewall spacers adjacent theperipheral NMOS transistor gate, implanting p-typeconductivity-enhancing dopant into the semiconductor material to formhalo regions operatively adjacent the peripheral NMOS source/drainregions.
 23. The method of claim 22 further comprising, after providingtransistor gates over the peripheral NMOS region and over the memoryarray region, and prior to providing sidewall spacers adjacent thesidewalls of the transistor gates, providing LDD regions operativelyadjacent the peripheral NMOS transistor gate and providing memory gatesource/drain regions operatively adjacent the memory NMOS transistorgates.
 24. The method of claim 22 further comprising: after forming haloregions operatively adjacent the NMOS source/drain regions, strippingthe masking layer from over the PMOS region and providing a maskinglayer over the peripheral NMOS region; after providing the masking layerover the NMOS region, etching the sidewall spacer material adjacent thePMOS transistor gate to decrease the lateral thickness of the sidewallspacers adjacent the PMOS transistor gate; and after decreasing thelateral thickness of the sidewall spacers adjacent the PMOS transistorgate, implanting n-type conductivity-enhancing dopant into thesemiconductor material to form halo regions operatively adjacent thePMOS transistor gate.
 25. The method of claim 24 further comprising,prior to decreasing the lateral thickness of the sidewall spacersadjacent the PMOS transistor gate and subsequent to stripping themasking layer from over the PMOS region, forming electrically conductivePMOS source/drain regions within the semiconductor material operativelyadjacent the PMOS transistor gate.
 26. The method of claim 22 furthercomprising: after forming halo regions operatively adjacent the NMOSsource/drain regions, stripping the masking layer from over the PMOSregion and providing a masking layer over the peripheral NMOS region;after providing the masking layer over the NMOS region, etching thesidewall spacer material adjacent the PMOS transistor gate to decreasethe lateral thickness of the sidewall spacers adjacent the PMOStransistor gate; and after decreasing the lateral thickness of thesidewall spacers adjacent the PMOS transistor gate, implanting p-typeconductivity-enhancing dopant into the semiconductor material to formLDD regions operatively adjacent the PMOS transistor gate.
 27. Themethod of claim 26 further comprising, prior to decreasing the lateralthickness of the sidewall spacers adjacent the PMOS transistor gate andsubsequent to stripping the masking layer from over the PMOS region,forming electrically conductive PMOS source/drain regions within thesemiconductor material operatively adjacent the PMOS transistor gate.28. The method of claim 22 further comprising: after forming theelectrically conductive peripheral NMOS source/drain regions, and priorto etching the sidewall spacer material adjacent the peripheral NMOStransistor gate, stripping the masking layer from over the PMOS region;etching the sidewall spacer material adjacent the PMOS transistor gateto decrease the lateral thickness of the sidewall spacers adjacent thePMOS transistor gate; and after decreasing the lateral thickness of thesidewall spacers adjacent the peripheral NMOS transistor gate and thePMOS transistor gate, blanket implanting the p-typeconductivity-enhancing dopant into the semiconductor material of boththe PMOS region and the NMOS region to form halo regions operativelyadjacent the NMOS transistor gate and to form PMOS LDD regionsoperatively adjacent the PMOS transistor gate.
 29. The method of claim28 further comprising, prior to decreasing the lateral thickness of thesidewall spacers adjacent the PMOS transistor gate and subsequent tostripping the masking layer from over the PMOS region, formingelectrically conductive PMOS source/drain regions within thesemiconductor material operatively adjacent the PMOS transistor gate.30. A semiconductor wafer comprising a peripheral NMOS and a memoryarray formed by the method of claim
 22. 31. A method for forming gradedjunction regions operatively adjacent a transistor gate, the methodcomprising the following steps: providing a semiconductor materialwafer; providing a transistor gate over the semiconductor materialwafer, the transistor gate having opposing lateral sidewalls; providingsidewall spacers adjacent the sidewalls of the transistor gate, thesidewall spacers having a lateral thickness and comprising a sidewallspacer material; decreasing the lateral thickness of the sidewallspacers by removing only a portion of the sidewall spacers; and afterdecreasing the lateral thickness of the sidewall spacers, implanting aconductivity-enhancing dopant into the semiconductor material to formgraded junction regions operatively adjacent the transistor gate. 32.The method of claim 31 wherein the semiconductor material wafercomprises an overall planar global configuration, the planar globalconfiguration establishing a virtual planar top surface and an axisnormal to the virtual planar top surface, and wherein the secondconductivity-enhancing dopant is implanted at an angle other thanparallel to the axis normal to the virtual planar top surface.
 33. Themethod of claim 31 further comprising, after providing the sidewallspacers and prior to decreasing the lateral thickness of the sidewallspacers, providing electrically conductive source/drain regionsoperatively adjacent the transistor gate.
 34. The method of claim 31further comprising incorporating the transistor gate into a PMOStransistor, wherein the implanted conductivity-enhancing dopant is ap-type dopant, and wherein the formed graded junction regions are LDDregions.
 35. The method of claim 31 further comprising incorporating thetransistor gate into a PMOS transistor, wherein the implantedconductivity-enhancing dopant is an n-type dopant, and wherein theformed graded junction regions are halo regions.
 36. The method of claim31 further comprising incorporating the transistor gate into an NMOStransistor, wherein the implanted conductivity-enhancing dopant is ap-type dopant, and wherein the formed graded junction regions are haloregions.
 37. The method of claim 31 further comprising incorporating thetransistor gate into an NMOS transistor, wherein the implantedconductivity-enhancing dopant is an n-type dopant, and wherein theformed graded junction regions are LDD regions.
 38. A transistor formedby the method of claim
 31. 39. A semiconductor transistor devicecomprising: a region of a semiconductor material wafer; a transistorgate over a portion of the region of the semiconductor material wafer,the transistor gate having opposing lateral sidewalls; opposingsource/drain regions operatively adjacent the transistor gate, eachsource/drain region having an inner lateral boundary; opposing sidewallspacers adjacent the sidewalls of the transistor gate, each sidewallspacer having an outer lateral edge, the sidewall spacers andsource/drain regions being paired such that the outer lateral edges ofthe sidewall spacers are displaced laterally inwardly relative to theinner lateral boundaries of the source/drain regions; and lateral gaps,the lateral gaps extending from the outer lateral edges of the sidewallspacers to the inner lateral boundaries of the source/drain regions. 40.The device of claim 39 wherein the lateral gaps have a length, thelength of the lateral gaps being from about 200 Angstroms to about 600Angstroms.
 41. The device of claim 39 further comprising graded junctionregions inwardly adjacent the source/drain regions, the graded junctionregions extending within the lateral gaps.
 42. A method for forming aperipheral NMOS transistor and one or more memory NMOS transistors, themethod comprising the following steps: forming a peripheral NMOStransistor gate and one or more memory NMOS transistor gates; formingsource/drain regions, halo regions and LDD regions operatively adjacentthe peripheral NMOS transistor gate, and forming source/drain regionsoperatively adjacent the one or more memory NMOS transistor gates, thesteps of forming the regions occurring in a sequence such that one ormore of the regions are formed last and are therefore last formedregions, wherein the LDD regions formed operatively adjacent theperipheral NMOS transistor gate are not the last formed regions; andless than two masking layer provision steps after the formation of theLDD regions operatively adjacent the peripheral NMOS transistor gate,and prior to formation of the one or more last formed regions.
 43. Amethod for forming graded junction regions operatively adjacent atransistor gate of CMOS circuitry, the method comprising the followingsteps: providing a semiconductor material wafer; defining a PMOS regionand an NMOS region of the wafer; providing a gate layer over the PMOSregion and over the NMOS region; patterning the gate layer over the NMOSregion to form an NMOS transistor gate over the NMOS region whileleaving the gate layer over the PMOS region unpatterned, the NMOStransistor gate having opposing lateral sidewalls; providing sidewallspacers adjacent the sidewalls of the NMOS transistor gate, the sidewallspacers having a lateral thickness and comprising a sidewall spacermaterial; after providing the sidewall spacers, forming electricallyconductive NMOS source/drain regions within the semiconductor materialoperatively adjacent the NMOS transistor gate; after forming theelectrically conductive NMOS source/drain regions, etching the sidewallspacer material adjacent the NMOS transistor gate to remove only aportion of said spacer material and to thereby decrease the lateralthickness of the sidewall spacers; and after decreasing the lateralthickness of the sidewall spacers adjacent the NMOS transistor gate,implanting conductivity-enhancing dopant into the semiconductor materialto thereby form NMOS graded junction regions operatively adjacent theNMOS source/drain regions.
 44. The method of claim 43 wherein theimplanted conductivity-enhancing dopant is a p-type dopant and whereinthe formed NMOS graded junction regions are halo regions.
 45. The methodof claim 43 wherein the portion of spacer material removed from thesidewall spacers constitutes no more than about 90% of the lateralthickness of the sidewall spacers adjacent the NMOS transistor gate. 46.The method of claim 43 wherein the gate layer comprises a polysiliconlayer, a refractory metal layer over the polysilicon layer, an oxidelayer over the refractory metal layer, and a silicon nitride layer overthe oxide layer.
 47. The method of claim 43 further comprising, afterforming the NMOS transistor gate, and prior to providing sidewallspacers, forming NMOS LDD regions operatively adjacent the NMOStransistor gate.
 48. The method of claim 43 wherein the opposing lateralsidewalls of the NMOS transistor gate comprise polysilicon, the methodfurther comprising: prior to providing sidewall spacers adjacent theNMOS transistor gate, oxidizing the polysilicon of the opposing lateralsidewalls to form an oxide layer along each opposing lateral sidewall.49. The method of claim 48 further comprising, after forming the NMOStransistor gate, and prior to providing the oxide layer along eachopposing lateral sidewall, forming NMOS LDD regions operatively adjacentthe NMOS transistor gate.
 50. The method of claim 43 wherein thesemiconductor material wafer comprises an overall planar globalconfiguration, the planar global configuration establishing a virtualplanar top surface and an axis normal to the virtual planar top surface,and wherein the p-type conductivity-enhancing dopant is implanted at anangle other than parallel to the axis normal to the virtual planar topsurface.
 51. The method of claim 43 further comprising: after formingthe NMOS transistor gate, patterning the gate layer over the PMOS regionto form a PMOS transistor gate over the PMOS region.
 52. A method forimplanting graded junction regions into a peripheral NMOS transistor andinto a memory array of NMOS transistors, the method comprising thefollowing steps: providing a semiconductor material wafer; defining amemory array region, a PMOS region and a peripheral NMOS region of thewafer; providing a gate layer over the PMOS, peripheral NMOS and memoryarray regions; patterning the gate layer over the peripheral NMOS regionto form a peripheral NMOS transistor gate over the peripheral NMOSregion, the peripheral NMOS transistor gate having opposing lateralsidewalls; patterning the gate layer over the memory array region toform an array of memory NMOS transistor gates over the memory arrayregion, the memory NMOS transistor gates having opposing lateralsidewalls; while patterning the gate layer over the peripheral NMOSregion, and while patterning the gate layer over the memory arrayregion, leaving the gate layer over the PMOS region unpatterned;providing sidewall spacers adjacent the sidewalls of the peripheral andmemory NMOS transistor gates, the sidewall spacers having a lateralthickness and comprising a sidewall spacer material; after providing thesidewall spacers forming electrically conductive peripheral NMOSsource/drain regions within the semiconductor material operativelyadjacent the peripheral NMOS transistor gate; after forming theelectrically conductive NMOS source/drain regions, etching the sidewallspacer material adjacent the peripheral NMOS transistor gate to removeonly a portion of said spacer material and to thereby decrease thelateral thickness of the sidewall spacers adjacent the peripheral NMOStransistor gate; and after decreasing the lateral thickness of thesidewall spacers adjacent the peripheral NMOS transistor gate,implanting conductivity-enhancing dopant into the semiconductor materialto form peripheral NMOS graded junction regions operatively adjacent theperipheral NMOS transistor gate.
 53. The method of claim 52 wherein thesemiconductor material wafer comprises an overall planar globalconfiguration, the planar global configuration establishing a virtualplanar top surface and an axis normal to the virtual planar top surface,and wherein the p-type conductivity-enhancing dopant is implanted at anangle other than parallel to the axis normal to the virtual planar topsurface.
 54. The method of claim 52 wherein the implantedconductivity-enhancing dopant is a p-type dopant and wherein the formedNMOS graded junction regions are halo regions.
 55. The method of claim52 further comprising, after providing sidewall spacers adjacent thesidewalls of the peripheral and memory NMOS transistor gates, and priorto forming electrically-conductive NMOS source/drain regions, providinga masking layer over the memory array region.
 56. The method of claim 52further comprising, after providing transistor gates over the peripheralNMOS region and over the memory array region, and prior to providingsidewall spacers adjacent the sidewalls of the transistor gates,providing LDD regions operatively adjacent the peripheral NMOStransistor gate and providing source/drain regions operatively adjacentthe memory NMOS transistor gates.
 57. The method of claim 52 wherein theopposing lateral sidewalls of the peripheral and memory NMOS transistorgates comprise polysilicon, the method further comprising: prior toproviding sidewall spacers adjacent the sidewalls of the peripheral andmemory NMOS transistor gates, oxidizing the polysilicon of the opposinglateral sidewalls to form an oxide layer along each of the opposinglateral sidewalls.
 58. The method of claim 57 further comprising, priorto providing the oxide layer along each lateral sidewall of theperipheral and memory NMOS transistor gates, forming peripheral NMOS LDDregions operatively adjacent the peripheral NMOS transistor gate andforming memory NMOS source/drain regions operatively adjacent the memoryNMOS transistor gates.
 59. The method of claim 52 further comprising:after forming halo regions operatively adjacent the NMOS source/drainregions, providing a masking layer over the peripheral NMOS region;after providing the masking layer over the peripheral NMOS region,patterning a PMOS transistor gate over the PMOS region; and formingelectrically conductive PMOS source/drain regions operatively adjacentthe PMOS transistor gate.
 60. The method of claim 59 further comprisingforming PMOS graded junction regions operatively adjacent the PMOSsource/drain regions.
 61. The method of claim 59 further comprisingforming PMOS graded junction regions operatively adjacent the PMOSsource/drain regions, wherein the PMOS graded junction regions areformed after the PMOS source/drain regions are formed.
 62. The method ofclaim 59 wherein the PMOS transistor gate has opposing lateralsidewalls, and further comprising: providing sidewall spacers adjacentthe sidewalls of the PMOS transistor gate, the sidewall spacers having alateral thickness and comprising a sidewall spacer material; afterforming the electrically conductive PMOS source/drain regions, etchingthe sidewall spacer material adjacent the PMOS transistor gate to removeonly a portion of said spacer material and to thereby decrease thelateral thickness of the sidewall spacers adjacent the PMOS transistorgate; and after decreasing the lateral thickness of the sidewall spacersadjacent the PMOS transistor gate, implanting conductivity-enhancingdopant into the semiconductor material of the PMOS region to form PMOSgraded junction regions operatively adjacent the PMOS transistor gate.63. The method of claim 59 wherein the PMOS transistor gate has a topand pair of opposing lateral sidewalls, and further comprising:providing an overhanging PMOS capping layer over the top of the PMOStransistor gate, the capping layer extending laterally outward beyondthe pair of opposing lateral sidewalls; after providing the cappinglayer, implanting p-type conductivity-enhancing dopant into thesemiconductor material of the PMOS region to form the electricallyconductive source/drain regions operatively adjacent the PMOS transistorgate, the overhanging capping layer offsetting the PMOS source/drainregions from the PMOS transistor gate; removing the overhanging cappinglayer from the top of the PMOS transistor gate; and implanting aconductivity-enhancing dopant into the semiconductor material of thePMOS region to form PMOS graded junction regions operatively adjacentthe PMOS source/drain regions.
 64. A method for forming graded junctionregions operatively adjacent a transistor gate, the method comprisingthe following steps: providing a semiconductor material wafer; providinga transistor gate over the semiconductor material wafer, the transistorgate comprising a layer of polysilicon and having opposing lateralsidewalls which include an exposed portion of the layer of polysilicon;forming an oxide layer along the exposed portion of the layer ofpolysilicon of the lateral sidewalls; providing sidewall spacersadjacent the sidewalls of the transistor gate and adjacent the oxidelayer, the sidewall spacers having a lateral thickness and comprising asidewall spacer material; after providing the sidewall spacers,implanting a first conductivity-enhancing dopant into the semiconductorwafer to form electrically conductive source/drain regions within thesemiconductor material operatively adjacent the transistor gate; afterforming the electrically conductive source/drain regions, etching thesidewall spacer material adjacent the transistor gate to remove saidsidewall spacers and to thereby expose the oxide layer; and afterexposing the oxide layer, implanting a second conductivity-enhancingdopant into the semiconductor material to form graded junction regionsoperatively adjacent the transistor gate.
 65. The method of claim 64further comprising, prior to forming the oxide layer along the exposedportion of the layer of polysilicon, forming graded junction regionsoperatively adjacent the transistor gate.
 66. The method of claim 64wherein the first conductivity-enhancing dopant is p-type, the secondconductivity-enhancing dopant is n-type, and the implant of the secondconductivity enhancing dopant forms halo regions.
 67. The method ofclaim 64 wherein the first conductivity-enhancing dopant is p-type, thesecond conductivity-enhancing dopant is p-type, and the implant of thesecond conductivity enhancing dopant forms LDD regions.
 68. The methodof claim 64 wherein the first conductivity-enhancing dopant is n-type,the second conductivity-enhancing dopant is n-type, and the implant ofthe second conductivity enhancing dopant forms LDD regions.
 69. Themethod of claim 64 wherein the first conductivity-enhancing dopant isn-type, the second conductivity-enhancing dopant is p-type, and theimplant of the second conductivity enhancing dopant forms halo regions.70. A method for forming a peripheral NMOS transistor and a memory arrayof NMOS transistors, the method comprising the following steps:providing a semiconductor material wafer; defining a memory arrayregion, a PMOS region and a peripheral NMOS region of the wafer;providing a gate layer over the PMOS, peripheral NMOS and memory arrayregions, the gate layer comprising a layer of polysilicon; patterningthe gate layer over the peripheral NMOS region to form a peripheral NMOStransistor gate, the peripheral NMOS transistor gate having opposinglateral sidewalls which include an exposed portion of the layer ofpolysilicon; patterning the gate layer over the memory array region toform an array of memory NMOS transistor gates over the memory arrayregion, the memory NMOS transistor gates having opposing lateralsidewalls which include an exposed portion of the layer of polysilicon;while patterning the gate layer over the peripheral NMOS region, andwhile patterning the gate layer over the memory array regions, leavingthe gate layer over the PMOS region unpatterned; forming an oxide layeralong the exposed portion of the layer of polysilicon of the lateralsidewalls of the peripheral NMOS transistor gate and along the exposedportions of the layer of polysilicon of the lateral sidewalls of thememory NMOS transistor gates; providing sidewall spacers adjacent thesidewalls of the peripheral and memory NMOS transistor gates andadjacent the oxide layers; after providing the sidewall spacers, formingelectrically conductive peripheral NMOS source/drain regions within thesemiconductor material operatively adjacent the peripheral NMOStransistor gate; after forming the electrically conductive NMOSsource/drain regions, removing the sidewall spacers from adjacent theperipheral NMOS transistor gate; and after removing the sidewallspacers, implanting conductivity-enhancing dopant into the semiconductormaterial to form peripheral NMOS graded junction regions operativelyadjacent the peripheral NMOS transistor gate.
 71. The method of claim 70further comprising, prior to forming the oxide layer along the exposedportion of the layer of polysilicon of the lateral sidewalls of theperipheral NMOS transistor gate and along the exposed portions of thelayer of polysilicon of the lateral sidewalls of the memory NMOStransistor gates, providing peripheral NMOS LDD regions operativelyadjacent the peripheral NMOS transistor gate and providingelectrically-conductive memory array source/drain operatively adjacentthe memory array transistor gates.
 72. The method of claim 70 whereinthe implant of conductivity-enhancing dopant into the semiconductormaterial comprises implanting p-type conductivity enhancing dopant andthereby forms peripheral NMOS halo regions operatively adjacent theperipheral NMOS transistor gate.
 73. The method of claim 70 furthercomprising, prior to forming the oxide layer along the exposed portionof the layer of polysilicon of the lateral sidewalls of the peripheralNMOS transistor gate and along the exposed portions of the layer ofpolysilicon of the lateral sidewalls of the memory NMOS transistorgates, providing peripheral NMOS LDD regions operatively adjacent theperipheral NMOS transistor gate and providing electrically-conductivememory array source/drain operatively adjacent the memory arraytransistor gates; and wherein the implant of conductivity-enhancingdopant into the semiconductor material comprises implanting p-typeconductivity enhancing dopant and thereby forms peripheral NMOS haloregions operatively adjacent the peripheral NMOS transistor gate. 74.The method of claim 70 further comprising, after providing sidewallspacers adjacent the sidewalls of the peripheral and memory NMOStransistor gates, and prior to forming electrically-conductive NMOSsource/drain regions, providing a masking layer over the memory arrayregion.
 75. The method of claim 70 further comprising: after formingperipheral NMOS graded junction regions operatively adjacent the NMOSsource/drain regions, patterning a PMOS transistor gate over the PMOSregion.
 76. A method for forming a transistor device, the methodcomprising the following steps: providing a semiconductor materialwafer, the semiconductor wafer having a surface; providing a transistorgate layer atop the surface of the semiconductor wafer, the transistorgate comprising an upper oxide layer and an insulative cap layer overthe upper oxide layer, the upper oxide layer having an upper surface,the upper oxide upper surface being at a level above the surface of thesemiconductor wafer, the insulative cap comprising an insulative capmaterial; providing a masking layer over the transistor gate and overthe surface of the semiconductor substrate, the masking layer having anupper surface and comprising a masking layer material; removing maskinglayer material from over the transistor gate until the masking layerupper surface is about level with the level of the upper surface of theupper oxide layer; and etching the insulative cap material to remove theinsulative cap from over the transistor gate to thereby expose the uppersurface of the upper oxide layer.
 77. The method of claim 76 wherein themasking layer material comprises photoresist.
 78. The method of claim 76wherein the insulative cap material comprises silicon nitride.
 79. Themethod of claim 76 wherein the transistor gate comprises opposinglateral sidewalls, the method further comprising: after forming thetransistor gate, providing sidewall spacers adjacent the opposinglateral sidewalls of the transistor gate, the sidewalls having a topsurface, the top surface of the sidewall spacers being elevationallyabove the upper surface of the upper oxide layer; and etching thesidewall spacers to form flat top surfaces of the sidewall spacers, theflat top surfaces being elevationally at about the same level as theexposed upper surface of the upper oxide layer of the transistor gate.80. The method of claim 76 wherein the transistor gate comprisesopposing lateral sidewalls, the method further comprising: after formingthe transistor gate, providing sidewall spacers adjacent the opposinglateral sidewalls of the transistor gate, the sidewalls having a topsurface, the top surface of the sidewall spacers being elevationallyabove the upper surface of the upper oxide layer, the sidewall spacerscomprising a sidewall spacer material which is identical to the materialof the insulative cap; and etching the sidewall spacer material to formflat top surfaces of the sidewall spacers, the flat top surfaces beingelevationally at about the same level as the exposed upper surface ofthe upper oxide layer of the transistor gate, the etching of thesidewall spacer material occurring concurrently with the etching of theinsulative cap material.
 81. The method of claim 80 wherein theinsulative cap material and the sidewall spacer material both comprisesilicon nitride.
 82. A method for forming CMOS circuitry, the methodcomprising the following steps: providing a semiconductor materialwafer, the semiconductor wafer having a surface; defining a PMOS regionand an NMOS region of the wafer; providing a gate layer over the PMOSregion and over the NMOS region, the gate layer having an upper oxidelayer and an insulative cap over the upper oxide layer, the upper oxidelayer having an upper surface, the upper oxide upper surface being at alevel above the surface of the semiconductor wafer, the insulative capcomprising an insulative cap material; patterning the gate layer overthe NMOS region to form an NMOS transistor gate over the NMOS regionwhile leaving the gate layer over the PMOS region unpatterned; providinga masking layer over the PMOS region and the NMOS region, the maskinglayer having an upper surface and comprising a masking layer material;removing masking layer material from over the PMOS and NMOS regionsuntil the masking layer upper surface is about level with the level ofthe upper surface of the upper oxide layer; and etching the insulativecap material to remove the insulative cap from over the NMOS gate andfrom over the unpatterned gate layer over the PMOS region to therebyexpose the upper surface of the upper oxide layer of the NMOS gate andto also thereby expose the upper surface of the upper oxide layer of theunpatterned gate layer over the PMOS region.
 83. The method of claim 82wherein the masking layer material comprises photoresist.
 84. The methodof claim 82 wherein the insulative cap material comprises siliconnitride.
 85. The method of claim 82 wherein the NMOS transistor gatecomprises opposing lateral sidewalls, the method further comprising:after forming the NMOS transistor gate, providing sidewall spacersadjacent the opposing lateral sidewalls of the NMOS transistor gate, thesidewalls having a top surface, the top surface of the sidewall spacersbeing elevationally above the upper surface of the upper oxide layer;and etching the sidewall spacers to form flat top surfaces of thesidewall spacers, the flat top surfaces being elevationally at about thesame level as the exposed upper surface of the upper oxide layer of theNMOS gate.
 86. The method of claim 82 wherein the NMOS transistor gatecomprises opposing lateral sidewalls, the method further comprising:after forming the NMOS transistor gate, providing sidewall spacersadjacent the opposing lateral sidewalls of the NMOS transistor gate, thesidewalls having a top surface, the top surface of the sidewall spacersbeing elevationally above the upper surface of the upper oxide layer,the sidewall spacers comprising a sidewall spacer material which isidentical to the material of the insulative cap; and etching thesidewall spacer material to form flat top surfaces of the sidewallspacers, the flat top surfaces being elevationally at about the samelevel as the exposed upper surface of the upper oxide layer of the NMOSgate, the etching of the sidewall spacer material occurring concurrentlywith the etching of the insulative cap material.
 87. The method of claim86 wherein the insulative cap material and the sidewall spacer materialboth comprise silicon nitride.
 88. A method for forming an NMOStransistor device and an insulated word line, the method comprising thefollowing steps: providing a semiconductor material wafer, thesemiconductor wafer having a surface; defining a memory array region ofthe wafer and a peripheral NMOS region of the wafer; providing a gatelayer over the peripheral NMOS and memory array regions of the wafer,the gate layer having an upper oxide layer and an insulative cap overthe upper oxide layer, the upper oxide layer having an upper surface,the upper oxide layer upper surface being at a level above the surfaceof the semiconductor wafer, the insulative cap comprising an insulativecap material; patterning the gate layer over the peripheral NMOS regionto form a peripheral NMOS transistor gate over the peripheral NMOSregion, the peripheral NMOS transistor gate having opposing lateralsidewalls; patterning the gate layer over the memory array region toform a word line, the word line having opposing lateral sidewalls;providing insulative sidewall spacers adjacent the opposing lateralsidewalls of the peripheral NMOS transistor gate and adjacent theopposing lateral sidewalls of the word line, the sidewall spacerscomprising a sidewall spacer material; providing a masking layer overthe peripheral NMOS region, the masking layer having an upper surfaceand comprising a masking layer material; removing the masking layermaterial from over peripheral NMOS region until the masking layer uppersurface is about level with the upper oxide layer upper surface; andremoving the insulative cap material from over the peripheral NMOStransistor gate to expose the upper oxide upper surface of theperipheral NMOS gate.
 89. The method of claim 88 further comprising:prior to removing the masking layer material from over the peripheralNMOS transistor gate, providing a masking layer over the word line, themasking layer over the word line comprising a masking layer materialidentical to the masking material of the masking layer over theperipheral NMOS transistor gate, the masking layer material over theword line having an upper surface which is elevationally above the uppersurface of the masking material over the peripheral NMOS transistorgate; and wherein the step of removing the masking layer material fromover peripheral NMOS region leaves masking layer material over the wordline.
 90. The method of claim 88 further comprising: prior to removingthe insulative cap from over the peripheral NMOS transistor gate,providing a masking layer over the word line.
 91. The method of claim 88further comprising: defining a PMOS region of the semiconductor materialwafer; providing the gate layer over the PMOS region; while patterningthe gate layer over the peripheral NMOS region, and while patterning thegate layer over the memory array region, leaving the gate layer over thePMOS region unpatterned; and while providing the masking layer over theperipheral NMOS region, also providing the masking layer over the PMOSregion.
 92. The method of claim 88 further comprising: defining a PMOSregion of the semiconductor material wafer; providing the gate layerover the PMOS region; while patterning the gate layer over theperipheral NMOS region, and while patterning the gate layer over thememory array region, leaving the gate layer over the PMOS regionunpatterned; while providing the masking layer over the peripheral NMOSregion, also providing the masking layer over the PMOS region; whereinthe step of removing the masking layer material from over peripheralNMOS region also removes masking layer material from over the PMOSregion; and wherein the step of removing the insulative cap materialfrom over the peripheral NMOS transistor gate to expose the upper oxideupper surface of the peripheral NMOS gate also removes insulative capmaterial from over the PMOS region to expose an upper oxide surface ofthe unpatterned masking material over the PMOS region.
 93. The method ofclaim 88 wherein the sidewall spacers of the peripheral NMOS transistorhave a top surface, the top surfaces of the sidewall spacers beingelevationally above the upper surface of the upper oxide layer of theperipheral NMOS transistor, the method further comprising: etching thesidewall spacers of the peripheral NMOS transistor to form flat topsurfaces of the sidewall spacers of the peripheral NMOS transistor, theflat top surfaces being elevationally at about the same level as theexposed upper surface of the upper oxide layer of the peripheral NMOSgate.
 94. The method of claim 88 wherein the sidewall spacers of theperipheral NMOS transistor have a top surface, the top surfaces of thesidewall spacers being elevationally above the upper surface of theupper oxide layer of the peripheral NMOS transistor, the method furthercomprising: etching the sidewall spacer material of the peripheral NMOStransistor to form flat top surfaces of the sidewall spacers of theperipheral NMOS transistor, the flat top surfaces being elevationally atabout the same level as the exposed upper surface of the upper oxidelayer of the peripheral NMOS gate, the etching of the sidewall spacermaterial occurring concurrently with the etching of the insulative capmaterial.
 95. The method of claim 88 further comprising patterning thegate layer over the memory array region to form memory transistor gates.96. The method of claim 88 wherein the insulative cap material and thesidewall spacer material both comprise silicon nitride.
 97. A method forforming a PMOS transistor device, a peripheral NMOS transistor device,and one or more memory NMOS transistor devices, the method comprisingthe following steps: providing a semiconductor material wafer; defininga PMOS region, a peripheral NMOS region, and a memory array region ofthe wafer; providing a gate layer over the PMOS, peripheral NMOS andmemory array regions; patterning the gate layer over the peripheral NMOSregion to form a peripheral NMOS transistor gate; patterning the gatelayer over the memory array region to form one or more memory arraytransistor gates; while patterning the gate layer over the peripheralNMOS and memory array regions, leaving the gate layer over the PMOSregion unpatterned; forming source/drain regions, halo regions and LDDregions operatively adjacent the peripheral NMOS transistor gate, andforming source/drain regions operatively adjacent the one or more memoryNMOS transistor gates, the steps of forming the regions occurring in asequence such that one or more of the regions are formed last and aretherefore last formed regions; and less than two masking layer provisionsteps after the formation of the peripheral NMOS transistor gate, andprior to the formation of the one or more last formed regions.
 98. Amethod of forming a transistor structure on a semiconductor substrate,comprising the following steps: providing a transistor gate assemblyformed on said substrate, said gate assembly including sidewall spacersextending to said substrate; doping a first region of said substratewith a selected dopant; removing a lateral portion of at least one ofsaid sidewall spacers, while leaving a part of said at least one of saidsidewall spacers in place; and after said removal, doping a secondportion of said substrate.